The present invention generally relates to level converting circuits, and more particularly to a level converting circuit which converts an ECL level which is used in an ECL circuit into a GaAs logic level which is used in a GaAs integrated circuit using a GaAs substrate.
In the field of compound semiconductor devices, there is a strong demand to realize an integrated circuit which uses a GaAs substrate and has a large integration density. However, it is difficult at the present to form a system solely of GaAs integrated circuits (or GaAs devices). For this reason, a system is formed by using GaAs devices together with ECL circuits or the like which operate at a high speed. In this case, it is necessary to provide in the system a level converting circuit for converting the ECL level which is used in the ECL circuits into the GaAs logic level which is used in the GaAs devices.
FIG. 1 shows an example of a conventional circuit arrangement for converting the ECL level into the GaAs logic level. In FIG. 1, an ECL device 1 is coupled to a GaAs device 2. The ECL device 1 includes an ECL internal gate circuit 3 and an ECL output buffer 4. On the other hand, the GaAs device 2 includes a GaAs input buffer 5 and a GaAs internal gate circuit 6. The ECL output buffer 4 is coupled to the GaAs input buffer 5. The GaAs input buffer 5 converts an output signal of the ECL output buffer 4 having the ECL level into a signal having the GaAs logic level and supplies the converted signal to the GaAs internal gate circuit 6.
FIG. 2 shows an example of the ECL output buffer 4. The ECL output buffer 4 includes transistors T1, T2, T3 and T9, and resistors R1, R2 and R3 which are connected as shown.
FIG. 3 shows an example of a buffer part of the GaAs input buffer 5. The buffer part includes transistors Tr1 through Tr4 which are connected in series between the power sources V.sub.DD and V.sub.SS. The logic signal V.sub.OUT from the ECL output buffer 4 is applied to a terminal 50, and an output signal of the buffer part is output via a terminal 51. The level converting circuit is provided within the GaAs input buffer 5 in addition to this buffer part shown in FIG. 3.
FIG. 4 shows an example of an interface circuit for providing the interface between the ECL device 1 and the GaAs device 2 and carrying out the necessary D.C. level conversion. The interface circuit corresponds to the buffer part of the GaAs input buffer 5 and includes transistors Tr21 through Tr28 and diodes D21 and D22 which are connected as shown. +V and -V respectively denote positive and negative power source voltages. The logic signal V.sub.OUT from the ECL output buffer 4 is applied to a terminal 70 and subjected to the D.C. level conversion in the interface circuit. A converted signal is output from a terminal 71 and is supplied to the GaAs internal gate circuit 6 within the GaAs device 2.
FIG. 5 shows an example of the GaAs internal gate circuit 6. The GaAs internal gate circuit 6 includes a transistor Tr11 which is connected to the power source GND and transistors Tr12 and Tr13 which are connected in series between the power sources V.sub.DD and GND. The output signal of the GaAs input buffer 5 is applied to a terminal 60, and an output signal of the GaAs internal gate circuit 6 is output via a terminal 61.
The ECL device 1 uses three power source voltages, namely, power source voltages V.sub.EE, V.sub.T and GND. V.sub.EE =-5.2 V, V.sub.T =-2 V and GND=0 V. On the other hand, the GaAs device 2 uses two power source voltages, namely, power source voltages V.sub.DD and GND. V.sub.DD =+2 V and GND=0 V. Hence, as a first method of providing an interface between the ECL device 1 and the GaAs device 2, the conventional circuit arrangement adds a negative power source voltage V.sub.SS in the GaAs device 2.
As a second method of providing an interface between the ECL device 1 and the GaAs device 2, the power source voltage V.sub.DD of the GaAs device 2 is set equal to GND=0 V of the ECL device 1 and the power source voltage GND of the GaAs device 2 is set equal to V.sub.T =-2 V of the ECL device 1.
In addition, as a third conceivable method of providing an interface between the ECL device 1 and the GaAs device 2, the power source voltage GND of the ECL device 1 is set equal to V.sub.DD =+2 V of the GaAs device 2 and the power source voltage V.sub.T of the ECL device 1 is set equal to GND=0 V of the GaAs device 2.
However, when the first method is used, a total of five power sources are required even when a common power source voltage is used as the power source voltages GND of the ECL device 1 and the GaAs device 2. As a result, there are problems in that the circuit becomes complex and it is troublesome and time consuming to design the complex circuit.
When the second method is used, there are problems in that the GaAs logic level becomes heavily dependent on the power source and it becomes impossible to provide an operating margin of the level converting circuit. These problems occur because the GaAs logic level of the GaAs device 2 is dependent on the lower power source voltage GND. In other words, when the lower power source voltage GND of the GaAs device 2 is replaced by the power source voltage V.sub.T (=-2 V) of the ECL device 1, the lower power source voltage GND easily fluctuates since the power source voltage V.sub.T of the ECL device 1 is easily affected by the ECL device 1.
On the other hand, when the third conceivable method is used, the operating margin of the level converting circuit is improved compared to the second method. However, since the power source voltage GND of the ECL device is replaced by the power source voltage V.sub.DD (=+2 V) of the GaAs device 2, the ECL device 1 itself becomes dependent on the power source voltage V.sub.DD of the GaAs device 2 and a new problem is introduced in that the margin of the ECL level becomes insufficient.
Furthermore, when one of the first through third methods is used, it is necessary to provide the ECL output buffer 4 in the ECL device 1 and to provide the GaAs input buffer 5 in the GaAs device 2. For this reason, the operation speed of the circuit arrangement is slowed down by the provision of the two buffers 4 and 5, and there is a problem in that it is difficult to realize a high speed operation.